A TV tuner needs to cover a wide reception band allocated to TV broadcast signals. For example, in Japan, a TV tuner needs to support VHF (Very High Frequency) channels (100 MHz band, 200 MHz band) and UHF (Ultra High Frequency) channels (470 MHz to 770 MHz). Also, a software radio needs to support a plurality of radio systems that use different radio bands.
In general, when a radio frequency signal of a frequency band that is an odd multiple of a local oscillation signal for driving a mixer is input to a mixer configuring a radio reception section, a disturbing signal frequency-converted to a frequency in the vicinity of received signal output having a desired frequency is output due to a nonlinear characteristic of the mixer (this disturbing signal is referred to below as odd-order harmonic response).
Here, if a reception band that should be supported by a TV tuner or software radio is wide, and the ratio between signal amplitude when a signal of a desired frequency is received and signal amplitude of other than a desired frequency component output due to harmonic response reaches a predetermined value, reception sensitivity degrades. Thus, technology is known that suppresses odd-order harmonic response by approximating an output waveform of a high-frequency component in mixer output to a sine wave (see Non-Patent Literature 1, for example).
FIG. 1 is a block diagram showing a conventional harmonic rejection mixer illustrated in FIG. 26.6.3 of Non-Patent Literature 1. As shown in FIG. 1, conventional harmonic rejection mixer 10 is provided with gm elements 1, 2, and 3, and mixers 4, 5, and 6, performs frequency conversion of a signal input from input terminal 11, and outputs the signal from output terminal 12.
These gm elements 1, 2, and 3 convert a voltage input from input terminal 11 to a current. Here, the ratio of an input voltage to output current of gm elements 1, 2, and 3 is set to gm1:gm2:gm3=1:√2:1.
Mixers 4, 5, and 6 are driven using control signals 21, 22, and 23 such as shown in FIG. 2. These control signals 21, 22, and 23 are pulse trains with the same frequency, a ratio of a Hi period (an on-period) to one cycle (hereinafter referred to as a duty ratio) of 50%, and phases shifted successively by 45°.
Thus, a high-frequency component output waveform such as shown in FIG. 3 is obtained by executing amplitude weighting by means of gin elements located in the respective paths after input signal branching, and adding and combining output signals of mixers driven by control signals with phases shifted successively by 45°. Since this output waveform approximates a sine wave, odd-order harmonic response can be suppressed.
In addition to above Non-Patent Literature 1, technology that suppresses harmonic response of a reception mixer used in a radio reception section by approximating an output waveform to a sine wave, and technology that suppresses harmonic distortion generated by a transmission mixer used in an amplifier or radio transmission section, are known (see Patent Literature 1 through Patent Literature 6, and Non-Patent Literature 2).
Here, as an example, a description will be given of harmonic rejection technology in a power amplifier described in Patent Literature 6. FIG. 4 is a configuration diagram of a power amplifier illustrated in FIG. 1A of Patent Literature 6. As shown in FIG. 4, power amplifier 50 is provided with amplifier circuit 51 and amplifier circuit 52, amplifies signals input from input terminal 61, input terminal 62, and input terminal 63, and outputs a signal from output terminal 64.
Amplifier circuit 51 has an inverter configuration comprising PMOS (Positive channel Metal Oxide Semiconductor) and NMOS (Negative channel Metal Oxide Semiconductor), in which a PMOS gate terminal is connected to input terminal 61 and an NMOS gate terminal is connected to input terminal 62, and the PMOS and NMOS are driven by independent input signals (input signal 55 and input signal 56). On the other hand, amplifier circuit 52 has an inverter configuration comprising PMOS and NMOS, in which the PMOS and NMOS gate terminals are connected to input terminal 63, and the PMOS and NMOS are driven by the same input signal (input signal 57).
FIG. 5 shows input signals 55, 56, and 57 input to power amplifier 50. Input signal 57 is a signal with a duty ratio of 50%, and is input to amplifier circuit 52 via input terminal 63. Input signal 55 is a signal that goes low during a Hi period of input signal 57 so that the operating time of the PMOS in amplifier circuit 51 is less than 50% of one cycle, and is input to the PMOS of amplifier circuit 51 via input terminal 61. Input signal 56 is a signal that goes high during a Low period of input signal 57 so that the operating time of the NMOS in amplifier circuit 51 is less than 50% of one cycle, and is input to the NMOS of amplifier circuit 51 via input terminal 62.
Here, by setting the transistor size ratio between amplifier circuit 51 driven by input signals 55 and 56 and amplifier circuit 52 driven by input signal 57 appropriately, the waveform of an output signal output via output terminal 64 (a signal obtained by adding the output signals of amplifier circuit 51 and amplifier circuit 52) can be approximated to a sine wave.